RNS Implementation of Two Dimensional Discrete Cosine Transform over FPL Devices

The FPL implementation of an 8×8 Two Dimensional Discrete Cosine Transform (2D-DCT) processor based on the Residue Number System (RNS) is presented in this paper. It makes use of a Fast Cosine Transform (FCT) algorithm that requires a single multiplication stage for each signal path, while most other algorithms include paths with more than one multiplication. The row-column decomposition technique is used and each 1D-DCT processor requires only 14 multipliers and 32 adders and subtractors. Performance and area were analysed through synthesis and simulation over Altera FLEX10KE FPL devices. The proposed RNSbased 2D-DCT processor provides a relevant throughput improvement compared to the equivalent 2’s complement system implementation when 8-bit moduli are used. Key-Words: Residue Number System, Discrete Cosine Transform, Field Programmable Logic.